Memory cells are circuits wherein information may be stored in a low current stand-by mode and may be written or read in a higher current mode. A predetermined number of cells are located in a row between each of a plurality of upper and lower word lines and another predetermined number of cells are located in a column between a plurality of bit lines. In other words, each cell is uniquely coupled between a combination of word lines and bit lines.
Conventionally, a row of cells is selected when increased voltage is supplied to the upper word line. A particular cell in that row is read by a sense amplifier coupled to the bit lines. A first read current through one bit line flows directly from the sense amplifier. A second read current through the other bit line flows through one side of the memory cell from the upper word line. When a cell is written, the first read current is directed through the cell and the second read current is directed from the sense amplifier.
The row rise time and therefore the row access time is limited by the AC response time of the cell, which if exceeded, will cause the cell to switch states (disturb). This limit can be improved for a given cell by reducing the row swing or by enhancing the response time of the cell.
The cell response time is conventionally improved by increasing the cell current when the row is selected. The typical selection circuit comprises an NPN transistor having a collector coupled to a supply voltage, an emitter coupled to the upper word line, and a base coupled to receive a selection signal input for supplying a high (selected) or low (deselected) signal to the NPN transistor. A standby current source is coupled between the lower word line and ground for continously providing current to the cell. A select current source is coupled between ground and the cathode of a diode. An anode of the diode is connected to the lower word line and steers current from the select current source to the lower word line only when the row is selected. Thus, the current from the select current source flows through the cell when the row is selected and enhances the response of the memory cell.
However, the above method is insufficient for memory cells having current levels determined by a bias regulator voltage applied to bases of PNP transistors serving as active loads of the memory cell. An additional means for biasing the active load transistors must be provided. Typically, a voltage source provides a bias voltage to the load transistor bases for each row of cells. Preferrably, this voltage source would be able to sense whether a given row of memory cells was selected and adjust the current levels of the active load transistors accordingly. However, such a voltage source would require a complex voltage regulator design.
Therefore, a circuit configuration is needed for selecting a row of bipolar memory cells that reduces selection time, eliminates the need for providing a regulated voltage for biasing an active load, and improves the memory cell response time.